Semiconductor packages and methods for forming the same

ABSTRACT

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 17/381,561 filed Jul. 21, 2021, which claims priority to U.S.provisional patent application Ser. No. 63/156,233, filed on Mar. 3,2021. Each of the afore mentioned patent application is incorporated byreference in its entirety.

BACKGROUND

The semiconductor industry continues to improve the integration densityof various electronic components (e.g., transistors, diodes, resistors,capacitors, etc.) by continual reductions in minimum feature size, whichallow more components, hence more functions, to be integrated into agiven area, forming integrated circuit dies. Each integrated circuit diemay include many input/output pads to communicate with other componentsto be packaged with the integrated circuit die. Interposers are commonlyused to provide input/output among two or more integrated circuit diesin a semiconductor package. However, integration density increases,connecting integrated circuit dies through interposers alone may becomechallenging.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1N schematically demonstrate a semiconductor device includingan integrated circuit die having edge interconnect features according toembodiments of the present disclosure.

FIGS. 2, 3A-3B, 4, and 5 schematically demonstrate various stages offorming a semiconductor package according to embodiments of the presentdisclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “over,” “top,” “upper” and the like, may be used herein forease of description to describe one element or feature's relationship toanother element(s) or feature(s) as illustrated in the figures. Thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

Embodiments discussed herein may be discussed in a specific context,namely a package structure (e.g., a package on package (PoP) structure)including dies bonded together with a hybrid bonding technique. The diescan be bonded together face-to-face (F2F) or face-to-back (F2B). Forexample, in a F2F bonding configuration the active surfaces (faces) ofthe dies are bonded together, whereas in a F2B bonding configuration, anactive surface of one die is bonded to a back surface of another die. Inaddition, the hybrid bonding between the dies includes adielectric-to-dielectric bonding and a metal bonding. For example, byincluding a solder bonding (instead of, for example, copper to copperbonding), the bonding temperature of the hybrid bonding can be loweredsignificantly.

Further, the teachings of this disclosure are applicable to any packagestructure including one or more semiconductor dies. Other embodimentscontemplate other applications, such as different package types ordifferent configurations that would be readily apparent to a person ofordinary skill in the art upon reading this disclosure. It should benoted that embodiments discussed herein may not necessarily illustrateevery component or feature that may be present in a structure. Forexample, multiples of a component may be omitted from a figure, such aswhen discussion of one of the components may be sufficient to conveyaspects of the embodiment. Further, method embodiments discussed hereinmay be discussed as being performed in a particular order; however,other method embodiments may be performed in any logical order.

Embodiments of the present disclosure provide an integrated circuit diehaving edge interconnect features. The edge interconnect features may beconductive lines extending through sealing rings and into scribe lineregions. In some embodiments, heterogeneous integrated circuit dies withedge interconnect features are fabricated on the same substrate. Edgeinterconnect features of the neighboring integrated circuit dies areconnected to each other and provide direct connections between theintegrated circuit dies without going through an interposer.

FIGS. 1A-1N schematically demonstrate an integrated circuit die havingedge interconnect features according to embodiments of the presentdisclosure. FIG. 1A is a schematic plan view of a substrate including anarray of integrated circuit dies according to the present disclosure.FIG. 1B is a schematic plan view of two neighboring integrated circuitdies 100 (100 a, 100 b) according to the present disclosure. FIG. 1C isan enlarged partial sectional view of the integrated circuit die 100along the line 1C-1C in FIG. 1B. FIG. 1D is an enlarged partialsectional view of the integrated circuit die 100 along the line 1D-1D inFIG. 1C. FIG. 1E is an enlarged partial sectional view of theneighboring integrated circuit die 100 a, 100 b along the line 1E-1E inFIG. 1B.

As shown in FIG. 1A, an array of integrated circuit dies (or chiplets)100 are formed on a substrate 10. The array of integrated circuit dies100 are separated from each other by two sets of intersecting scribelines 12. One set of scribe lines 12 extend along the x-direction and asecond set of scribe lines 12 extend along the y-direction. The array ofintegrated circuit dies 100 are formed in and/or on the substrate 10within an array of areas defined by the scribe lines 12. In someembodiments, the integrated circuit dies 100 including two or moredifferent circuit designs. After fabrication, the integrated circuitdies 100, may be tested and cut out along the scribe lines 12 toindividual integrated circuit dies 100 or various combination ofneighboring integrated circuit dies 100 for subsequent processing, suchas packaging.

As shown in FIG. 1A, the plurality of integrated circuit dies 100fabricated in and/or on the substrate 10 include two types of integratedcircuit dies 100 a, 100 b. The integrated circuit dies 100 a, 100 b mayhave substantially the same dimension but with different circuit designsto achieve different functions. In some embodiments, the integratedcircuit dies 100 a, 100 b are arranged alternatively so that each of theintegrated circuit die 100 a is bordered by at least one integratedcircuit die 100 b. Neighboring integrated circuit dies 100 a, 100 b areconnected through edge interconnect features as discussed below.

As shown in FIG. 1A, each of the integrated circuit die 100 (100 a, 100b) may include a circuit region 104 (104 a, 104 b) surrounded by a sealregion 106 (106 a, 106 b). According to embodiments of the presentdisclosure, the integrated circuit die 100 (100 a, 100 b) includes oneor more edge interconnect features 108 (108 a, 108 b) extending from thecircuit region 104 (104 a, 104 b) through the seal region 106 (106 a,106 b) into the scribe line 12. In some embodiments, the edgeinterconnect features 108 may be conductive lines intersecting with thescribe lines 12 surrounding the integrated circuit die 100 (100 a, 100b). After the integrated circuit die 100 (100 a, 100 b) is cut out alongthe scribe lines 12, the edge interconnect features 108 (108 a, 108 b)are exposed on cutting surfaces 102 of the integrated circuit die 100(100 a, 100 b). The edge interconnect features 108 (108 a, 108 b) may beconductive lines configured to connect with external contacts formed onthe cutting surfaces 102 (102 a, 102 b) to provide signal and/or powersupplies.

In some embodiments, the edge interconnect features 108 (108 a, 108 b)may be symmetrically arranged across all scribe lines 12 around theintegrated circuit die 100 (100 a, 100 b). The symmetrical arrangementprovides high feasibility for circuit designers. One connection protocolfor the edge interconnect features may be used in different integratedcircuit dies, thus, facilitating fabrication of two or more directlyconnected integrated circuit dies on one substrate. For example, in FIG.1A, a plurality of pairs of directly connected integrated circuit dies100 a, 100 b are fabricated in and on the substrate 10. In someembodiments, individual integrated circuit dies 100 a, 100 b may betested before cutting. The integrated circuit dies 100 a, 100 b may becut into various die combinations, such as die combinations 16 a, 16 b,16 c, 16 d, for packaging, thus lowering cost of production. For the diecombinations 16 a, 16 b, which include single integrated circuit dies100 a, 100 b, conductive features may be formed from the exposed edgeinterconnect features 108 to connect with other integrated circuit dieswithout going through an interposer. The die combinations 16 c, 16 d,which includes the integrated circuit dies 100 a, 100 b of differentarrangements, may be directly packaged as connected components withoutcutting out as individual dies.

The substrate 10 may be a semiconductor substrate, for example, bulksilicon, doped or undoped, or an active layer of asemiconductor-on-insulator (SOI) substrate. The semiconductor substratemay include other semiconductor material, such as germanium; a compoundsemiconductor including silicon carbide, gallium arsenic, galliumphosphide, indium phosphide, indium arsenide, and/or indium antimonide;an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs,GaInP, and/or GaInAsP; or combinations thereof. Other substrates, suchas a multi-layered or gradient substrate may also be used.

The array of integrated circuit dies 100 may be formed in and/or on thesubstrate 10 by performing various semiconductor fabrication processes,including, but not limited to, front-end-of-line (FEOL) processing, andback-end-of-line (BEOL) processing. As shown in FIGS. 1C, 1D, and 1E,the various semiconductor fabrication processes are performed to form adevice layer 120 (120 a, 120 b) and an interconnect structure 122 (122a, 122 b) in the integrated circuit dies 100 (100 a, 100 b).

In some embodiments, the array of integrated circuit dies 100 mayinclude two or more different circuit designs formed on the samesubstrate 10 to achieve direct heterogenous connections between theintegrated circuit dies 100. In other embodiments, the array ofintegrated circuit dies 100 have substantially identical circuitdesigns, which may be cut off individually to be connected to othercircuit components through the edge interconnect features 108.

The integrated circuit dies 100 may be designed to perform any suitablefunction. For example, the integrated circuit die 100 may be a logic die(e.g., central processing unit, a SoC, ASIC, FPGA, microcontroller,etc.), a memory die (e.g., a DRAM die, a Wide I/O die, a M-RAM die, aR-RAM die, a NAND die, an SRAM die, etc.), a memory cube (e.g., HBM,HMC, etc.), a high data rate transceiver die, an I/O interface die, anintegrated passive device die (e.g., an IPD die), a power management die(e.g., a PMIC die), an RF die, a sensor die, an MEMS die, signalprocessing dies (e.g., a DSP die), a front-end die (e.g., an AFE dies),a monolithic 3D heterogeneous chiplet stacking die, the like, or acombination thereof.

FIG. 1B is a schematic plan view of two neighboring integrated circuitdies 100 a, 100 b according to the present disclosure formed on thesubstrate 10. In FIG. 1B, components formed in various layers along thez-axis are superimposed on one another to show their relative positionsin plan view. Positions of the components along the z-axis are showncorresponding cross-sectional views, such as the views in FIGS. 1C and1D. FIG. 1B illustrates relative positions of the circuit region 104,the seal region 106, and the edge interconnect features 108 within theintegrated circuit dies 100 according to some embodiments. As shown inFIG. 1B, each integrated circuit die 100 is defined in a square area bythe scribe lines 12. In some embodiments, the integrated circuit dies100 may have a plan view area in a range between about 10 mm² and about1000 mm² depending on the circuit design and/or function of theintegrated circuit die 100. FIG. 1B illustrates integrated circuit dieswith a square shape in the plan view. However, the integrated circuitdies may have other shapes in the plan view. For example, rectangular,hexagonal, octagonal shapes may be used to achieve design purposes.Depending on the design, the scribe lines 12 may have a width 12 w in arange between about 1 μm to about 200 μm. A scribe line width 12 w lowerthan 1 μm may not be wide enough to tolerant system errors duringseparation of the integrated circuit dies 100. A scribe line width 12 wgreater than 200 μm would increase cost of production without additionalbenefit.

Within the die area of each integrated circuit die 100, the circuitregion 104 is surrounded by the seal region 106 around an outerperimeter of the circuit region 104. One or more sealing rings 110, 112are concentrically formed in the seal region 106. The seal rings 110,112 provide protection to circuit structures in the circuit region 104against undesired elements from the exterior environment, such as watervapor, during and after separation of the integrated circuit dies 100.

Even though two sealing rings 110, 112 are shown in the integratedcircuit die 100, less or more sealing rings may be included in the sealregion 106. After being cut along the scribe lines 12, the portion ofthe scribe line 12 may remain on sides of the integrated circuit die100, and the seal region 106 is surrounded by materials of the scribelines 12 and not exposed on the cutting surfaces 102.

The edge interconnect features 108 are two or more conductive linesextending from the circuit region 104 through the seal region tointersect with the scribe lines 12. In some embodiments, the edgeinterconnect features 108 may intersect with the corresponding scribeline 12 at a substantially perpendicular manner. In other embodiments,the edge interconnect features 108 may intersect with the correspondingscribe line 12 at a slanted angle. For example, the edge interconnectfeatures 108 may intersect the y-z plan at a slanted angle, such as anangle in a range between about 45 degree to about 90 degree. In someembodiments, the edge interconnect features 108 may be distributed alongone or more of sides 106 s of the seal region 106. In some embodiments,the edge interconnect features 108 are a plurality of conductive linesdistributed along one or more of the sides 106 s. In some embodiments,the plurality of conductive lines may be evenly distributed along one ormore sides 106 s of the seal region 106.

In some embodiments, as shown in FIG. 1B, the edge interconnect features108 may be symmetrically arranged along all sides 106 s of the sealregion 106. For example, an equal number of the edge interconnectfeatures 108 are distributed alone every sides 106 s of the seal region106 at a substantially equal pitch. The symmetrical distribution allowcorresponding edge interconnect features 108 in neighboring integratedcircuit dies 100 to form continuous conductive lines. As shown in FIG.1B, edge interconnect features 108 a of the integrated circuit die 100 aare in contact with corresponding edge interconnect features 108 b ofthe integrated circuit die 100 a to form a plurality of continuousconductive lines across the shared scribe line 12. Similarly, the edgeinterconnect features 108 a along other sides 106 s of the seal region106 may form continuous line features with corresponding edgeinterconnect features 108 in the neighboring integrated circuit die 100along the other sides 106 s.

In some embodiments, the edge interconnect features 108 a of theintegrated circuit die 100 a and the corresponding edge interconnectfeatures 108 b of the integrated circuit die 100 b are fabricated asmonolithic conductive lines. The monolithic conductive line arrangementmay enable direct communication between devices in the neighboringintegrated circuit dies, and thus, allowing the neighboring integratedcircuit dies to be packaged together without cutting from the scribelines. The monolithic conductive line arrangement also provides highertolerance to the cutting operation and ensures that the edgeinterconnect features 108 are exposed on the cutting surface 102.

The continuous line features ensure that the edge interconnect features108 are exposed on the cutting surfaces 102 for subsequent wiring andpackaging process after the integrated circuit die 100 is cut free fromthe substrate 10. The symmetrical arrangement of the edge interconnectfeatures 108 also provide design flexibilities. For example, a commonscheme of edge interconnect feature arrangement may be used fordifferent integrated circuit dies, such as for different SoCs, anddifferent memory dies. It should be noted that the edge interconnectfeatures 108 may be arranged in any suitable manner to achieve desireddesign proposes.

FIGS. 1C and 1D provide additional details of the edge interconnectfeatures 108 within the integrated circuit die 100 according toembodiments of the present disclosure. FIG. 1C schematically illustratesdetails across the seal region 106 of the integrated circuit die 100.FIG. 1D schematically illustrates details of the integrated circuit die100 along the sealing ring 110. FIG. 1E schematically illustratesdetails adjacent the scribe line 12 between the integrated circuit dies100 a, 100 b.

As shown in FIGS. 1C and 1D, the device layer 120 is formed in and/or onthe substrate 10, and the interconnect structure 122 are formed over thedevice layer 120. The device layer 120 may include various semiconductordevices, such as transistors, diodes, capacitors, resistors, etc., andmay be formed in and/or on the substrate 10. In some embodiments, thedevice layer 120 includes one or more dielectric layers overlying thesemiconductor devices therein.

The interconnection structure 122 includes various conductive features,such as a first plurality of conductive features 126 and secondplurality of conductive features 128, and one or more intermetaldielectric (IMD) layers 124 to separate and isolate various neighboringconductive features 126, 128. In some embodiments, the first pluralityof conductive features 126 are conductive vias and the second pluralityof conductive features 128 are conductive lines. The interconnectionstructure 122 includes multiple levels of the conductive features 128,and the conductive features 128 are arranged in each level to provideelectrical paths to the devices in the device layer 120. The conductivefeatures 126 provide vertical electrical routing from the device layer120 to the conductive features 128, and between the conductive features128 in different layers.

The conductive features 126 and conductive features 128 may be made fromone or more electrically conductive materials, such as one or morelayers of graphene, metal, metal alloy, metal nitride, or silicide. Forexample, the conductive features 126 and the conductive features 128 aremade from copper, aluminum, aluminum copper alloy, titanium, titaniumnitride, tantalum, tantalum nitride, titanium silicon nitride,zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride,tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, othersuitable conductive material, or a combination thereof.

The IMD layers 124 may be formed, for example, of a low dielectricconstant (low-K) dielectric material, such as SiOx, SiOxCyHz, SiOxCy,SiCx, SiNx, or related low-k dielectric material, compounds thereof,composites thereof, combinations thereof, or the like. The IMD layers124 may be formed by any suitable method, such as spinning, chemicalvapor deposition (CVD), and/or plasma-enhanced CVD (PECVD). In someembodiments, the interconnect structure 122 may be formed sequentiallylayer-by-layer from the device layer 120 during BOEL processing. In someembodiments, the interconnect structure 122, the conductive features 126and conductive features 128 may be fabricated using damascene and/ordual-damascene process.

As shown in FIG. 1C, a plurality of IMD layers 124 are sequentiallyformed over the device layer 120 with the conductive features 126, 128having increased dimension. The number of IMD layers 124 may be anynumber suitable for the circuit design. For example, the number of IMDlayers 124 may be between 1 and 30. In FIG. 1C, the IMD layers 124 aredivided into three groups: bottom IMD layers 124 x, middle IMD layers124 y, top IMD layers 124 z based on relative position to the devicelayer 120. The bottom IMD layers 124 x, formed immediately on the devicelayer 120 are thinner and with the conductive features 126, 128 of ahigher density. The middle IMD layers 124 y formed over the bottom IMDlayers 124 x are thicker and with the conductive features 126, 128 of alower density. The top IMD layers 124 z formed over the middle IMDlayers 124 y are thickest and with the conductive features 126, 128 of alowest density.

The sealing rings 110, 112 are formed in the seal region 106 between thecircuit region 104 and the scribe line 12. Each of the sealing rings110, 112 includes physically connected components to function as abarrier between the conductive features 126, 128 in the interconnectstructure 122 and exterior environment, such as moisture. The sealingrings 110, 112 may be formed by any suitable designs and with anysuitable materials, such as materials suitable as moisture barrier. Insome embodiments, the sealing rings 110, 112 are formed withelectrically conductive materials. In some embodiments, the sealingrings 110, 112 may be electrically grounded. In some embodiments, thesealing rings 110, 112 may be formed from the same material as theconductive features 126, 128. For example, the sealing rings 110, 112may be formed from Cu, Al, Co, Ru, Mo, W, and related alloys.

FIGS. 1C and 1D schematically demonstrate one example of the sealingrings 110, 112. Other sealing ring structures may be used by personsskilled in the art with the integrated circuit die 100 according topresent disclosure. As shown in FIGS. 1C and 1D, each of the sealingrings 110, 112 includes layers of substantially continuous sealing lines1101, 1121 connected by a plurality of sealing vias 110 v, 112 v formedin the IMD layers 124. The continuous sealing lines 1101, 1121 inneighboring IMD layers 124 are connected by the plurality of sealingvias 110 v, 112 v respectively. The sealing lines 1101, 1121 and sealingvias 110 v, 112 v may be fabricated layer-by-layer in the same processwith the conductive features 126, 128 in the corresponding IMD layers124. Dimension of the sealing lines 1101, 1121 may vary in different IMDlayers 124. In some embodiments, the sealing lines 1101, 1121 may have aline width 106 w in a range between about 0.01 μm and about 6 μm, and aline depth 106 d in a range between about 0.01 μm and about 6 μm.

The edge interconnect features 108 may be formed in one or more IMDlayers 124. Each of the edge interconnect features 108 may be conductiveline having an inner end 108 i and an outer end 1080. The inner end 108i may be electrically connected to one or more conductive features 128,126 in the circuit region 104. The outer end 108 o is embedded in thescribe line 12 outside the seal region 106. In some embodiments, aportion of the edge interconnect features 108 may be dummy connectors toachieve structural uniformity in the integrated circuit die 100. Forexample, the inner end 108 i of a portion of the edge interconnectfeatures 108 may be “floating” in the IMD layer 124 without connectingto any other conductive features, such as conductive features 126, 128.If the integrated circuit die 100 is cut out along the scribe line 12,the outer ends 108 o of the edge interconnect features 108 is exposed onthe cutting surface 102.

In some embodiments, the integrated circuit die 100 may be designed toconnect with two or more other integrated circuit dies through the edgeinterconnect features 108. In some embodiments, some of the edgeinterconnect features 108 may be assigned to provide connections to oneof the other integrated circuit dies. For example, a first portion ofthe edge interconnect features 108 a along one side of 102 of theintegrated circuit die 100 a may be designated to provide connectionwith the integrated circuit die 100 b, and a second portion of the edgeinterconnect features 108 a may be designated to provide connection withan integrated circuit die 100 c, with different circuit designs from theintegrated circuit dies 100 a, 100 b.

The edge interconnect features 108 extend through the sealing rings 110,112 through openings 130 which are formed in the sealing ring 110, 112and the corresponding IMD layer 124. Dielectric material of the IMDlayer 124 is disposed between the edge interconnect features 108 and thesealing rings 110, 112 to electrically isolate the edge interconnectfeatures 108 from the sealing rings 110, 112.

The edge interconnect features 108 may be formed in the same processwith the conductive features 126, 128 in the corresponding IMD layers124. In some embodiments, the sealing rings 110, 112 may be formed fromthe same material as the conductive features 126, 128. For example, theedge interconnect features 108 may be formed from Cu, Al, Co, Ru, Mo, W,and related alloys.

In some embodiments, dimensions of the edge interconnect features 108may be similar to the conductive features 128 in the same IMD layer 124.In some embodiments, the edge interconnect features 108 may have a linewidth 108 w in a range between about 0.01 μm and about 6 μm, and a linedepth 108 d in a range between about 0.01 μm and about 6 μm. A width 130w of the openings 130 may be in a range between about 0.03 μm and about18 μm.

Dimension of the edge interconnect features 108 may vary in differentIMD layers 124. Depending on the function and density of the edgeinterconnect features 108, the edge interconnect features 108 may beformed in the bottom IMD layers 124 x, the middle IMD layers 124 y, thetop IMD layers 124 z, and a top metal layer (not shown) above the topIMD layer 124 z. For example, if the edge interconnect features 108 areused to transfer signals to individual devices in the device layer 120,the density of the edge interconnect features 108 is likely to berelatively high and the width of the edge interconnect features 108 maybe relatively small, and the edge interconnect features 108 may beformed in one or more bottom IMD layers 124 x. If the edge interconnectfeatures 108 are used to provide power supply to the device layer 120,the density of the edge interconnect features 108 is likely to berelatively low and the width of the edge interconnect features 108 maybe relatively large, and the edge interconnect features 108 may beformed in one or more top IMD layers 124 z.

In some embodiments, the scribe lines 12 between the integrated circuitdies 100 may also be filled with suitable materials. A dielectricmaterial may be filled in the scribe lines 12 between the integratedcircuit dies 100. The outer end 108 o of the edge interconnect features108 are surrounded by the dielectric material in the scribe lines 12,thus, are electrically isolated from one another. In some embodiments,the scribe lines 12 may be filled with the same material as in the IMDlayers 124. The scribe lines 12 may be filled and then patternedlayer-by-layer in the same process with the conductive features 126, 128in the corresponding IMD layers 124. In some embodiments, the scribelines 12 or the dielectric material filled in the scribe lines 12 mayinclude one or more layers of a low dielectric constant (low-K)dielectric material, such as SiOx, SiOxCyHz, SiOxCy, SiCx, SiNx, orrelated low-k dielectric material, compounds thereof, compositesthereof, combinations thereof, or the like.

FIG. 1E schematically illustrates that each of the edge interconnectfeatures 108 a of the integrated circuit die 100 a and the correspondingedge interconnect features 108 b of the integrated circuit die 100 bform a continuous conductive line 1081 across the scribe line 12 betweenthe inter circuit dies 100 a, 100 b. The scribe line 12 may includemultiple layers of suitable materials formed on the substrate 10 betweenthe seal regions 106 a, 106 b of the neighboring integrated circuit dies102 a, 102 b. In some embodiments, the scribe line 12 may be formedlayer-by-layer during the fabrication process of the device layer 120 a,120 b and the interconnect structures 122 a, 122 b. Layers in the scribeline 12 may include the same materials of the dielectric layers 124 inthe interconnect structures 122 a, 122 b. In some embodiments, thescribe line 12 may also include one or more dielectric layers betweenthe device layers 120 a, 120 b. In other embodiments, the scribe line 12may be formed separately from the interconnect structures 122 a, 122 band/or the device layers 120 a, 120 b by suitable processes, such aspatterning, deposition, and etching. Materials in the scribe line 12 maybe different from the dielectric layers 124 in the interconnectstructures 122 a, 122 b.

A plurality of conductive lines 1081 are formed across the scribe line12 between the neighboring integrated circuit dies 100 a, 100 b. Aportion of the plurality of the conductive lines 1081 are functionalconnections with both ends connected to the conductive features 126/128in the integrated circuit dies 100 a, 100 a. In some embodiments, aportion of the conductive lines 1081 may be dummy connection with atleast one end “floating” in the corresponding integrated circuit die 100a or 100 b.

In the embodiment shown in FIGS. 1C, 1D, and 1E, the edge interconnectfeatures 108 are formed in the top IMD layer 124 z. As discussed above,the edge interconnect features 108 according to the present disclosuremay be formed in any suitable IMD layers.

FIG. 1F is an enlarged partial sectional view of the integrated circuitdie 100, according to another embodiment, along the line 1C-1C in FIG.1B. FIG. 1G is an enlarged partial sectional view of the integratedcircuit die 100 along the line 1G-1G in FIG. 1F. FIG. 1H is an enlargedpartial sectional view of the neighboring integrated circuit die 100 a,100 b along the line 1E-1E in FIG. 1B corresponding to the embodimentshown in FIGS. 1F and 1G. In the embodiment shown in FIGS. 1F, 1G, and1H, the edge interconnect features 108 are formed in the middle IMDlayer 124 y.

FIG. 1I is an enlarged partial sectional view of the integrated circuitdie 100, according to another embodiment, along the line 1C-1C in FIG.1B. FIG. 1J is an enlarged partial sectional view of the integratedcircuit die 100 along the line 1J-1J in FIG. 1I. FIG. 1K is an enlargedpartial sectional view of the neighboring integrated circuit die 100 a,100 b along the line 1E-1E in FIG. 1B corresponding to the embodimentshown in FIGS. 11 and 1J. In the embodiment shown in FIGS. 1I, 1J, and1K, the edge interconnect features 108 are formed in the bottom IMDlayer 124 x.

FIG. 1L is an enlarged partial sectional view of the integrated circuitdie 100, according to another embodiment, along the line 1C-1C in FIG.1B. FIG. 1M is an enlarged partial sectional view of the integratedcircuit die 100 along the line 1M-1M in FIG. 1L. FIG. 1N is an enlargedpartial sectional view of the neighboring integrated circuit die 100 a,100 b along the line 1E-1E in FIG. 1B corresponding to the embodimentshown in FIGS. 1L and 1M. In the embodiment shown in FIGS. 1L, 1M and1N, the edge interconnect features 108 are formed in a dielectricmaterial. In some embodiments, the dielectric material may include twoor more IMD layers 124. Particularly, in FIGS. 1L, 1M, and 1N, the edgeinterconnect features 108 are formed in one of the bottom IMD layer 124x and in one of the top IMD layer 124 z. It should be noted that theedge interconnect features 108 may be formed in any combination of IMDlayers 124.

FIG. 2 is schematic plan views of a substrate 20 having an array ofintegrated circuit dies 100′ formed thereon. The array of integratedcircuit dies 100′ are separated from each other by two sets ofintersecting scribe lines 22. The plurality of integrated circuit dies100 fabricated in and/or on the substrate 20 include three types ofintegrated circuit dies 100 a, 100 b, 100 c. Similar to the integratedcircuit die 100 a, 100 b, the integrated circuit die 100 c includes edgeinterconnect features 108 c extending through seal region 106 c to thescribe lines 22.

The integrated circuit dies 100 a, 100 b, 100 c may have substantiallythe same dimension but with different circuit designs to achievedifferent functions. In some embodiments, the integrated circuit dies100 a, 100 b, 100 c may be different types of dies to be connected invarious combinations.

In the example of FIG. 2 , the integrated circuit die 100 a may bedesigned to connect with both the integrated circuit die 100 b andintegrated circuit die 100 c. The integrated circuit dies 100 a, 100 b,100 c are arranged in a pattern so that each of the integrated circuitdie 100 b is bordered by at least one integrated circuit die 100 a, andeach of the integrated circuit die 100 c is bordered by at least oneintegrated circuit die 100 a. Neighboring integrated circuit dies 100 a,100 b are connected through the edge interconnect features 108 a, 108 b.Neighboring integrated circuit dies 100 a, 100 c are connected throughthe edge interconnect features 108 a, 108 c.

In some embodiments, the edge interconnect features 108 (108 a, 108 b,108 c) may be symmetrically arranged across all scribe lines 22 aroundthe integrated circuit die 100 (100 a, 100 b, 100 c) and share the sameprotocol so that the integrated circuit dies 100 a, 100 b, 100 c candirectly connect with one other through the edge interconnect features108 a, 108 b, 108 c.

In some embodiments, a first portion of the edge interconnected feature108 a in the integrated circuit die 100 a are designated to connect tothe edge interconnect features 108 b in the integrated circuit die 100b, and a second portion of the edge interconnected feature 108 a in theintegrated circuit die 100 a are designated to connect to the edgeinterconnect features 108 c in the integrated circuit die 100 c. Thefirst portion and second portion the edge interconnected features 108 amay be mutual exclusive or include shared members depending on thecircuit design.

Individual integrated circuit dies 100 a, 100 b, 100 c may be testedbefore cutting. The integrated circuit dies 100 a, 100 b, 100 c may becut into various die combinations, such as die combinations 26 a, 26 b,26 c, 26 d, 26 e, 26 f, 26 g for packaging, thus lowering cost ofproduction. For the die combinations 26 a, 26 b, 26 c which includesingle integrated circuit dies 100 a, 100 b, 100 c conductive featuresmay be formed from the exposed edge interconnect features 108 to connectwith other integrated circuit dies without going through an interposer.The die combinations 16 d, 16 e, which includes the two integratedcircuit dies 100 a/100 c or 100 a/100 b, may be directly packaged asconnected components. The die combinations 26 f, 26 g, which includesthe three integrated circuit dies 100 a, 100 b, 100 c of in differentarrangement may be directly packaged as connected components.

FIGS. 3A-3D, 4A-4D, 5A-5B, 6, and 7 schematically demonstrate variousstages of forming a semiconductor package 300 according to embodimentsof the present disclosure. The semiconductor package 300 includes adirectly connected die combination with two or more integrated circuitdies formed on the same substrate and connected through edgeinterconnect features according to the present disclosure.

FIG. 3A is a schematic plan view of the semiconductor package 300. FIG.3B is a schematic cross-sectional view of the semiconductor package 300.In FIG. 3A, the semiconductor package 300 includes the die combination26 f, which includes three integrated circuit dies 100 b, 100 a, 100 cformed in and/or the substrate 20 and connected by the edge interconnectfeatures 108 a, 108 b, 108 c formed in the scribe line 22.

As discussed in FIG. 2 , the die combination 26 f may be fabricated byfabricating the array of integrated circuit dies 100 including theintegrated circuit dies 100 b, 100 a, 100 c in a suitable pattern,testing individual integrated circuit dies 100 a, 100 b, 100 c, and thencutting out a die combination including good and connected integratedcircuit dies 100 b, 100 a, 100 c. The die combination 26 f is only anexample. Other die combinations, such as the die combination 26 g may beused in place of the die combination 26 g to perform the same function.Die combinations with different sets of integrated circuit dies may beused to fabricate semiconductor packages for other functions.

In some embodiments, the integrated circuit dies 100 a, 100 b, 100 c mayinclude any suitable circuit designs that may be fabricated on the samesubstrate. For example, each of the integrated circuit dies 100 a, 100b, 100 c may be a system on a chip (SOC) or a system on integratedcircuit (SOIC) die; a memory die, such as a static random-access memory(SRAM) die, a dynamic random-access memory (DRAM) die, a high bandwidthmemory (HBM) die, or the like; a passive device die, such as amultilayer ceramic chip (MLCC) capacitor die, an integrated passivedevice (IPD) die, an integrated voltage regulator (IVR) die, the like,or a combination thereof; a logic die; an analog die; amicroelectromechanical system (MEMS) die, a radio frequency (RF) die, ora combination thereof. In some embodiments, the integrated circuit dies100 a, 100 b, 100 c may be interconnected through edge interconnectfeatures and intended to function as a die combination without cuttingaway from one another when connected integrated circuit dies 100 a, 100b, 100 c all pass test. In some embodiments, when an integrated circuitdie 100 a, 100 b, 100 c on a substrate fail the test, the failedintegrated circuit die 100 a, 100 b, 100 c is cut out leavingneighboring integrated circuit dies 100 a, 100 b, 100 c to form a diecombination with other dies. In some embodiments, the integrated circuitdies 100 a, 100 b, 100 c may be three different SOCs.

As shown in FIG. 3A, each of the integrated circuit die 100 a, 100 b,100 c includes the circuit region 104 a, 104 b, 104 c surrounded by theone or more sealing rings 110 a/112 a, 110 b/112 b, 110 c/112 a. Theedge interconnect features 108 a, 108 b, 108 c extend from thecorresponding circuit region 104 a, 104 b, 104 c through the regions ofthe sealing rings 110 a/112 a, 110 b/112 b, 110 c/112 c into the scribelines 22.

The scribe line 22 may include multiple layers of suitable materialsformed on the substrate 20 surrounding the sealing rings 110 a/112 a,110 b/112 b, 110 c/112 c of the integrated circuit dies 102 a, 102 b,106 c. In some embodiments, the scribe line 22 may be formedlayer-by-layer during the fabrication process of the device layers 120a, 120 b, 120 c and the interconnect structures 122 a, 122 b, 122 c.Layers in the scribe line 22 may include the same materials of thedielectric layers in the interconnect structures 122 a, 122 b, 122 c. Insome embodiments, the scribe line 22 may also include one or moredielectric layers between the device layers 120 a, 120 b, 120 c. Inother embodiments, the scribe line 22 may be formed separately from theinterconnect structures 122 a, 122 b, 122 c and/or the device layers 120a, 120 b, 120 c by suitable processes, such as patterning, deposition,and etching. Materials in the scribe line 22 may be different from thedielectric layers in the interconnect structures 122 a, 122 b, 122 c.

As shown in FIG. 3B, the edge interconnect features 108 b, 108 a in thescribe line 22 between the integrated circuit dies 100 b, 100 a formcontinuous conductive lines to provide direct electric connectionstherebetween, and the edge interconnect features 108 a, 108 c in thescribe line 22 between the integrated circuit dies 100 a, 100 c formcontinuous conductive lines to provide direct electric connectionstherebetween.

As shown in FIGS. 3A and 3B, the die combination 26 f is attached to acarrier substrate 302. In some embodiments, an adhesive layer 304 isformed on the carrier substrate 302, and a die attach film 306 is formedon the adhesive layer 304. The die combination 26 f is attached on thedie attach film 306. The carrier substrate 302 may be a glass carriersubstrate, a ceramic carrier substrate, or the like. In someembodiments, multiple semiconductor packages can be formed on thecarrier substrate 302 simultaneously.

The adhesive layer 304 is placed on the carrier substrate 302 to assistin the adherence of overlying structures, for example, the diecombination 26 f. In some embodiments, the adhesive layer 304 maycomprise a light to heat conversion (LTHC) material or an ultra-violetglue, although other types of adhesives, such as pressure sensitiveadhesives, radiation curable adhesives, epoxies, combinations of these,or the like, may also be used. The adhesive layer 304 may be placed ontothe carrier substrate 302 in a semi-liquid or gel form, which is readilydeformable under pressure. In other embodiments, the adhesive layer 304may be an ultra-violet (UV) glue, which loses its adhesive property whenexposed to UV lights.

The die attach film 306 may be placed on the adhesive layer 304 toassist in the attachment of the die combination 26 f to the adhesivelayer 304. In some embodiments, the first die attach film 306 may be anepoxy resin, a phenol resin, acrylic rubber, silica filler, or acombination thereof, and is applied using a lamination technique. Thedie attach film 306 may be dispensed as a liquid and cured, may be alaminate film laminated onto the carrier substrate 302, or may be thelike. In some embodiments, the top surface of the die attach film 306may be leveled and may have a high degree of coplanarity. However, anyother suitable alternative material and method of formation mayalternatively be utilized.

The die combination 26 f may be placed onto the die attach film 306. Thedie combination 26 f may be placed using, e.g., a pick and placeprocess, in a face-up orientation. However, any suitable method ofplacing the die combination 26 f onto the die attach film 306 may alsobe utilized.

After the die combination 26 f is attached to the carrier substrate 302,an encapsulant layer 312 is formed over various components, includingthe die combination 26 f, on the carrier substrate 302, as shown in FIG.4 . FIG. 4 is a schematic cross-sectional view of the semiconductorpackage 300.

The encapsulant layer 312 may be a molding compound, epoxy, or the like,and may be applied by compression molding, lamination, transfer molding,or the like. The encapsulant layer 312 may be formed over the carriersubstrate 302 such that cutting surfaces of the die combination 26 f areburied or covered. The encapsulant layer 312 may then be cured.

In some embodiments, the encapsulant layer 312 may undergo a grindingprocess to expose conductive features on the integrated circuit dies 100a, 100 b, 100 c so that external contacts 314 may be formed. Theexternal contacts 314 may be formed on the integrated circuit dies 100a, 100 b, 100 c, for example, by a bumping process. The externalcontacts 314 may be, e.g., conductive pillars such as a copper pillarsor copper posts. In some embodiments, the external contacts 314 may besolder bumps, copper bumps, or other suitable external contacts that maybe made to provide electrical connection from the integrated circuitdies 100 a, 100 b, 100 c to other external devices. All such externalcontacts are fully intended to be included within the scope of theembodiments. As the edge interconnect features 108 a, 108 b, 108 cprovide internal connections between or among the integrated circuitdies 100 a, 100 b, 100 c, the external contacts 314 may be used toprovide external connections to the integrated circuit dies 100 a, 100b, 100 c.

In some embodiments, an optional interposer substrate 316 may beattached to the external contacts 314. The interposer substrate 316 mayinclude various embedded interconnections, which may provide routes fromthe external contacts 314 to external circuits, such as a printedcircuit board. In other embodiments, the external contacts 314 may besubsequently connected to a printed circuit board.

An encapsulant layer 318 may then be formed over the interposersubstrate 316. The encapsulant layer 318 may be a molding compound,epoxy, or the like, and may be applied by compression molding,lamination, transfer molding, or the like. The encapsulant layer 318 maybe formed over the interposer substrate 316 such that the externalcontacts 314 are buried or covered. The encapsulant layer 318 may thenbe cured. In some embodiments, the encapsulant layer 318 and theencapsulant layer 312 may be formed from the same material.

In some embodiments, the encapsulant layer 318 may undergo a grindingprocess to expose conductive features on the interposer substrate 316.External connectors 320 are then formed on the interposer substrate 316.The external connectors 320 may be used to connect the semiconductorpackage 300 to a printed wiring board or printed circuit board (PCB) toform an electronic assembly. In some embodiments, through substrate viasor TSVs 317 extend vertically through the interposer substrate 316 andelectrically connect the external connectors 320 and the externalcontacts 314. In some embodiments, the TSVs 317 may be through siliconvias where a silicon substrate material is used. TSVs 317 may be made ofany suitable conductive material commonly used in the art for such vias,including without limitation tungsten, copper, nickel, or alloysthereof. In some representative embodiments, TSVs 317 may have arepresentative diameter, without limitation, of about 5 microns to about12 microns depending on the design requirement and process used to formthe TSVs 317.

FIG. 5 schematic cross-sectional view of the semiconductor package 300attached to a PCB 322, with the carrier substrate 302 along with theadhesive layer 304 and the die attach film 306 removed. The PCB 322 maybe part of an electronic assembly can be part of an electronic systemsuch as computers, wireless communication devices, computer-relatedperipherals, entertainment devices, or the like.

Even though three integrated circuit dies 100 a, 100 b, 100 c are shownin the semiconductor package 300, less or more integrated circuit dieswith edge interconnect features may be packaged together according tocircuit design.

Embodiments of the present disclosure provide an integrated circuit diewith edge interconnect features extending from one or more IMD layersacross a scribe line to another integrated circuit die. The edgeinterconnect features of different integrated circuit dies providedirect connection between the integrated circuit dies. The directconnection between different integrated circuit dies reduces interposerlayers, redistribution process, and bumping processes in multi-dieintegration, thus, reducing cost of manufacturing. The edge interconnectfeatures also enable power to be directly transferred therethrough,instead of going through interposer substrates, or PCBs, thus achievehigher performance. The edge interconnect features, connected to one ormore IMD layers, also enables higher routing density than through aninterposer. The edge interconnect features design may be easily adoptedfrom one integrated circuit die to another, thus, provide highfeasibility and flexibility for designers.

Some embodiments of the present provide a semiconductor device,comprising a first integrated circuit die comprising a first sealingring encircling a first circuit region, a second integrated circuit diecomprising a second sealing ring encircling a second circuit region, adielectric layer formed between the first sealing ring and the secondsealing ring. and a conductive line extending from the first circuitregion to the second circuit region through the first sealing ring, thedielectric layer, and the second sealing ring.

Some embodiments of the present disclosure provide an integrated circuitdie. The integrated circuit die includes a device layer comprising oneor more semiconductor devices, an interconnect structure formed on thedevice layer, wherein the interconnect structure comprises a dielectriclayer, a sealing ring formed in the dielectric layer encircling acircuit region within the dielectric layer, and one or more conductivefeatures embedded in the circuit region of the dielectric layer, whereinthe one or more conductive features are connected to one or moresemiconductor devices in the device layer, and a plurality of edgeinterconnect features formed in the dielectric layer, wherein theplurality of edge interconnect features extending outwards from thecircuit region through the sealing ring.

Some embodiments of the present disclosure provide a method for forminga semiconductor device. The method includes forming a first integratedcircuit die having a first edge interconnect feature, and a secondintegrated circuit die having a second edge interconnect feature on asubstrate, wherein a scribe line is formed between the first and secondintegrated circuit dies, and the first edge interconnect featureconnected to the second edge interconnect feature in the scribe line;and attaching the first and second integrated circuit dies to a printedcircuit board with the first and second circuit dies remaining connectedto each other the scribe line.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A semiconductor device, comprising: a first integrated circuit diecomprising a first sealing ring encircling a first circuit region; asecond integrated circuit die comprising a second sealing ringencircling a second circuit region; a dielectric layer formed betweenthe first sealing ring and the second sealing ring; and a conductiveline extending from the first circuit region to the second circuitregion through the first sealing ring, the dielectric layer, and thesecond sealing ring.
 2. The semiconductor device of claim 1, wherein thefirst integrated circuit die further comprises a first interconnectstructure, and the conductive line is connected to the firstinterconnect structure.
 3. The semiconductor device of claim 2, whereinthe first interconnect structure comprises: an IMD (inter metaldielectric) layer; and a conductive feature embedded in the IMD layer,wherein the conductive line is connected to the conductive feature. 4.The semiconductor device of claim 3, wherein the conductive line extendsbetween sections of the first sealing ring.
 5. The semiconductor deviceof claim 1, further comprising a substrate, wherein the first integratedcircuit die, the dielectric layer and the second integrated circuit dieare formed on the substrate.
 6. The semiconductor device of claim 2,wherein the first integrated circuit die further comprises a pluralityof external contacts formed on the first interconnect structure.
 7. Thesemiconductor device of claim 6, further comprising an interposersubstrate attached to the plurality of external contacts of the firstintegrated circuit die.
 8. An integrated circuit die, comprising: adevice layer comprising one or more semiconductor devices; aninterconnect structure formed on the device layer, wherein theinterconnect structure comprises: a dielectric layer; a sealing ringformed in the dielectric layer encircling a circuit region within thedielectric layer; and one or more conductive features embedded in thecircuit region of the dielectric layer, wherein the one or moreconductive features are connected to one or more semiconductor devicesin the device layer; and a plurality of edge interconnect featuresformed in the dielectric layer, wherein the plurality of edgeinterconnect features extending outwards from the circuit region throughthe sealing ring.
 9. The integrated circuit die of claim 8, wherein atleast a portion of the plurality of edge interconnect features areelectrically connected to the one or more conductive features.
 10. Theintegrated circuit die of claim 9, wherein the sealing ring is arectangle ring, and the plurality of edge interconnect features aresymmetrically distributed along four sides of the rectangle ring. 11.The integrated circuit die of claim 10, wherein a portion of thedielectric layer is formed outside the sealing ring, and the pluralityof edge interconnect features extend across the sealing ring.
 12. Theintegrated circuit die of claim 8, wherein the plurality of edgeinterconnect features extending between sections of the sealing ring.13. The integrated circuit die of claim 8, wherein the interconnectstructure further comprises a second dielectric layer, and a secondplurality of edge interconnect features formed in the second dielectriclayer.
 14. The integrated circuit die of claim 8, wherein the pluralityof edge interconnect features are connected to conductive features in aneighboring integrated circuit die.
 15. A semiconductor package,comprising: a first integrated circuit die and a second integratedcircuit die formed on a substrate and divided by a scribe line, whereinthe first integrated circuit die has a first edge interconnect feature,and the second integrated circuit die has a second edge interconnectfeature, and the first edge interconnect feature are connected to thesecond edge interconnect feature across the scribe line; and a printedcircuit board, wherein with the first and second circuit dies are bondedto the printed circuit board while remaining connected to each other atthe scribe line.
 16. The semiconductor package of claim 15, wherein eachof the first and second integrated circuit dies comprises: a devicelayer including one or more semiconductor devices; and an interconnectstructure over the device layer, wherein the interconnect structureincludes one or more IMD layers, and the first and second edgeinterconnect features are embedded in the one or more IMD layers. 17.The semiconductor package of claim 16, wherein each of the first andsecond integrated circuit dies further comprises: one or more sealingrings surrounding the interconnect structure, wherein the first edgeinterconnect feature and the second edge interconnect feature extendthrough the one or more sealing rings.
 18. The semiconductor package ofclaim 15, further comprising an interposer bonded to the first andsecond integrated circuit dies through plurality of external contacts.19. The semiconductor package of claim 15, wherein the first integratedcircuit die includes comprises a plurality of edge interconnect featuressymmetrically distributed along four edges of the first integratedcircuit die, and the second circuit die is disposed along a first edgeof the four edges of the first integrated circuit die.
 20. Thesemiconductor package of claim 19, further comprising: a thirdintegrated circuit die disposed along a second edge of the four edges ofthe first integrated circuit die, wherein at one of the plurality offirst edge interconnect features extends from the first die to the thirdintegrated circuit die.